A semiconductor device having the structure of a power MOSFET, in which gate trenches and source trenches are formed, has been widely applied in recent years to various power supplies such as DC—DC converters. FIG. 11 shows an example of such a semiconductor device. FIG. 11 is a sectional view showing an example of a semiconductor device according to conventional technology. In FIG. 11, a semiconductor device 300 comprises an N+ type drain layer 301, an N− type drift layer 302, a P type body layer 303, P+ type diffusion areas 304, a source electrode film 305, gate insulating films 306, gate electrode films 307, a drain electrode film 309, gate trenches 311, N+ type source areas 312, source trenches 313, an insulating film 319, and a PSG film 320. “W” refers to the width of the mesa.
To form the semiconductor device 300, the N− type drift layer 302 is laminated on the N+ type drain layer 301, and then the P type body layer 303 and the N+ type source area 312 are laminated on the N− type drift layer 302. The gate trenches 311 are formed so as to extend from the surface of the N+ type source area 312 to the N− type drift layer 302. Furthermore, the source trenches 313 are formed so as to extend from the surface of the N+ type source area 312 to the P type body layer 303. The gate trenches 311 and the source trenches 313 are alternately disposed in parallel with each other. The gate insulating film 306 is formed in the bottom and side faces of the gate trench 311. The gate insulating film 306 makes contact with the P type body layer 303 and the N+ type source areas 312. The gate electrode film 307 is formed on the inner surface of the gate insulating film 306 in such a manner as to charge the space, surrounded by the gate insulating film 306. The gate electrode film 307 is electrically insulated from the P type body layer 303 and the N+ type source areas 312 by the gate insulating film 306.
In addition, the insulating film 319 is formed so as to cover the surfaces of the gate insulating films 306, the gate electrode films 307, and the N+ type source areas 312. Furthermore, the surface of the insulating film 319 is covered with the PSG (phospho-silicate glass) film 320. The source electrode film 305 is formed on the inner surfaces of the source trenches 313 and the surface of the PSG film 320. The source electrode film 305 makes contact with the N+ type source areas 312 and the P+ type diffusion areas 304. The drain electrode film 309 is formed on the surface of the N+ type drain layer 301 on which the N− type drift layer 302 is not formed.
In the semiconductor device 300, when a voltage is applied between the source electrode film 305 and the drain electrode film 309, and a voltage having a threshold value or more is applied between the gate electrode film 307 and the source electrode film 305, inversion layers are formed in the vicinity of the borders between the P type body layer 303 and the gate insulating films 306. The inversion layers become channels. Electric current flows from the drain electrode film 309 to the source electrode film 305 through these channels. On the other hand, when the voltage applied between the gate electrode film 307 and the source electrode film 305 is reduced to the threshold value or less, on the other hand, the channels disappear. Then, the electric current ceases to flow between the source electrode film 305 and the drain electrode film 309.
Since the source trenches 313 are formed in the semiconductor device 300, as described above, the N+ type source areas 312 are electrically connected to the source electrode film 305 inside the source trenches 313. Thus, consideration of the design, by which a certain degree of the area of the top faces (surfaces) of the N+ type source areas 312 has to be secured for connection with the source electrode film 305, becomes unnecessary. Also, since the P+ type diffusion areas 304 are formed in the P type body layer 303, there is the advantage that the area of the top faces of the N+ type source areas 312 can be reduced as compared with a case where the P+ type diffusion areas 304 are formed on the surfaces of the N+ type source areas 312 by diffusion. Such a semiconductor device is disclosed in Japanese Patent Laid-Open Publication No. 2000-223708.
To miniaturize such a semiconductor device, it is necessary to reduce the width of mesa “W.” When, for example, the width of mesa “W” is reduced to 0.5 μm or less, the P+ type diffusion area 304 tends to make contact with the gate trench 311. This is a consequence of the precision of semiconductor production equipment for forming the source trenches 313 and the P+ type diffusion areas 304, this being equipment such as that used in a photographic process. Such a semiconductor device cannot be used since it exhibits electric characteristics, which a designer does not plan. Therefore, this problem related to the width of mesa “W” has become a significant factor preventing the miniaturization of such semiconductor devices.
Considering the foregoing circumstances, an object of the present invention is to provide a semiconductor device, in which gate trenches and source trenches are formed, having an easily miniaturized structure.